View CY7C343_205350.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

USE ULTRA37000TM FOR ALL NEW DESIGNS
CY7C343
64-Macrocell MAX(R) EPLD
Features
* 64 MAX(R) macrocells in four LABs * Eightdedicated inputs, 24 bidirectional I/O pins * Programmable interconnect array * 0.8-micron double-metal CMOS EPROM technology * Available in 44-pin HLCC, PLCC * Lowest power MAX device
Functional Description
The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are eight input pins, one that doubles as a clock pin when needed. The CY7C343 also has 28 I/O pins, each connected to a macrocell (six for LABs A and C, and eight for LABs B and D). The remaining 36 macrocells are used for embedded logic. The CY7C343 is excellent for a wide range of both synchronous and asynchronous applications.
Logic Block Diagram 9 INPUT
11 INPUT 12 INPUT 13 INPUT DEDICATED INPUTS SYSTEM CLOCK LAB A 2 4 5 6 7 8 MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELLS 7-16
INPUT 35 INPUT/CLK 34 INPUT 33 INPUT 31
LAB D MACROCELL 56 MACROCELL 55 MACROCELL 54 MACROCELL 53 MACROCELL 52 MACROCELL 51 MACROCELL 50 MACROCELL 49 1 44 42 41 40 39 38 37
I/O PINS
I/O PINS
LAB B 15 16 17 18 19 20 22 23 MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22 MACROCELL 23 MACROCELL 24 MACROCELLS 25-32 (3, 14, 25, 36) (10, 21, 32, 43)
P I A
MACROCELLS 57-64 LAB C MACROCELL 38 MACROCELL 37 MACROCELL 36 MACROCELL 35 MACROCELL 34 MACROCELL 33
I/O PINS
30 29 28 27 26 24
I/O PINS
MACROCELLS 39-48
VCC GND
Selection Guide
Maximum Access Time Maximum Operating Current 7C343-20 20 135 225 225 125 200 200 7C343-25 25 135 225 225 125 200 200 7C343-30 30 135 225 225 125 200 200 7C343-35 35 135 225 225 125 200 200 Unit ns mA
Maximum Standby Current
Commercial Military Industrial Commercial Military Industrial
mA
Cypress Semiconductor Corporation Document #: 38-03015 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 22, 2004
USE ULTRA37000TM FOR ALL NEW DESIGNS
Pin Configuration
HLCC, PLCC Top View
GND V CC I/O I/O I/O I/O I/O I/O I/O I/O I/O
CY7C343
6 I/O I/O INPUT GND INPUT INPUT INPUT VCC I/O I/O I/O 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 I/O I/O I/O VCC INPUT INPUT/CLK INPUT GND INPUT I/O I/O
7C343
31 30 29
18 19 20 21 22 23 24 25 26 27 28 GND I/O I/O I/O I/O I/O I/O I/O I/O V CC I/O
Document #: 38-03015 Rev. *B
Page 2 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
CY7C343
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from a straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on the input pins. tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAH) is less than 1/(tAS2 + tAH). When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same clock as the CY7C343. In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous), then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device's register.
Timing Delays
Timing delays within the CY7C343 may be easily determined using Warp(R), Warp ProfessionalTM, or Warp EnterpriseTM software. The CY7C343 has fixed internal delays, allowing the user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C343 contains circuitry to protect device pins from high static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.
Document #: 38-03015 Rev. *B
Page 3 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
EXPANDER DELAY tEXP
CY7C343
REGISTER OUTPUT DELAY tOD tXZ tZX
INPUT INPUT DELAY tIN
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
tCLR tPRE tRSU tRH tRD tCOMB tLATCH
INPUT/ OUTPUT
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC
FEEDBACK DELAY tFD
I/O DELAY tIO
Figure 1. CY7C343 Internal Timing Model
Document #: 38-03015 Rev. *B
Page 4 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to +150C Ambient Temperature with Power Applied.................................................. 0C to +70C Maximum Junction Temperature (Under Bias)................................................................. 150C Supply Voltage to Ground Potential ............... -2.0V to +7.0V Maximum Power Dissipation...................................2500 mW DC VCC or GND Current ............................................500 mA Electrical Characteristics Over the Operating Range[3] Parameter VOH VOL VIH VIL IIX IOZ IOS ICC1 ICC2 tR tF Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current[6] Recommended Input Rise Time Recommended Input Fall Time GND < VIN < VCC VO = VCC or GND VCC = Max., VOUT = VI = VCC or GND (No Load) VI = VCC or GND (No Load) f = 1.0 MHz[5, 6] 0.5V[4, 5] Commercial Military/Industrial Commercial Military/Industrial Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8 mA 2.2 -0.3 -10 -40 -30 Min. 2.4
CY7C343
DC Output Current, per Pin ......................-25 mA to +25 mA DC Input Voltage[1] .........................................-3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage........................................... > 1100V (per MIL-STD-883, method 3015)
Operating Range[2]
Range Commercial Industrial Military Ambient Temperature 0C to +70C -40C to +85C -55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%
Max. 0.45 VCC + 0.3 0.8 +10 +40 -90 125 200 135 225 100 100
Unit V V V V A A mA mA mA mA mA ns ns
Capacitance[7]
Parameter CIN COUT
R1 464 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: OUTPUT R2 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 163 1.75V
Notes: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns. 2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 3. Typical values are for TA = 25C and VCC = 5V. 4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 5. Guaranteed but not 100% tested. 6. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material. 7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
Description Input Capacitance Output Capacitance
Test Conditions VIN = 2V, f = 1.0 MHz VOUT = 2.0V, f = 1.0 MHz
R1 464
Max. 10 10
Unit pF pF
AC Test Loads and Waveforms[7]
ALL INPUT PULSES 3.0V R2 250 10% GND < 6 ns 90% 90% 10% < 6 ns
(a)
(b)
THEVENIN EQUIVALENT (commercial/military)
Document #: 38-03015 Rev. *B
Page 5 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Synchronous Switching Characteristics Over Operating Range [7]
7C343-20 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS1 tS2 tH tWH tWL tRW tRR tRO Description Dedicated Input to Combinatorial Output Delay[8] I/O Input to Combinatorial Output Delay[9] Com'l/Ind Mil Com'l/Ind Mil Dedicated Input to Combinatorial Output Delay with Expander Com'l/Ind Delay[10] Mil
11]
CY7C343
7C343-25 Min. Max. 25 25 39 39 37 37 51 51 25 25 25 25 14 14 30 30 15 15 30 30 0 0 8 8 8 8 25 25 25 25 ns 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Min.
Max. 20 20 32 32 30 30 42 42 20 20 20 20 12 12 25
I/O Input to Combinatorial Output Delay with Expander Delay[5, Com'l/Ind Input to Output Enable Delay[5, 8] Input to Output Disable Delay[5, 8] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[5, 12] Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[8] I/O Input Set-Up Time to Synchronous Clock Input[8, 13] Input Hold Time from Synchronous Clock Input[8] Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Asynchronous Clear Width[5, 8] Asynchronous Clear Recovery Time[5, 8] Asynchronous Clear to Registered Output Delay[8] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 24 24 0 0 6 6 6 6 20 20 20 20 12
20 20
Notes: 8. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 9. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 10. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 12. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 13. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation..
Document #: 38-03015 Rev. *B
Page 6 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20 Parameter tPR tPO tCF tP fMAX1 fMAX2 fMAX3 fMAX4 tOH tPW Description Asynchronous Preset Recovery Time
[5, 8]
CY7C343
7C343-25 Min. 25 25 20 20 3 3 12 12 41.6 41.6 66.6 66.6 83.3 83.3 83.3 83.3 3 3 20 20 16 16 34 34 55 55 62.5 62.5 62.5 62.5 3 3 25 25 ns ns MHz MHz MHz MHz 25 25 3 3 ns ns ns Max. Unit ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 20 20
Max.
Asynchronous Preset to Registered Output Delay[8] Synchronous Clock to Local Feedback Input[5, 14] External Synchronous Clock Period (1/fMAX3)[5] External Maximum Frequency (1/(tCO1 + tS1))[5, 15]
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 Com'l/Ind + tCF)) or (1/tCO1)[5, 16] Mil Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), Com'l/Ind or (1/tCO1)[5, 17] Mil Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18] Output Data Stable Time from Synchronous Clock Input[5, 19] Asynchronous Preset Width[5, 8] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
Notes: 14. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 15. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. 16. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local, originating within the same LAB.. 17. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to dedicated inputs and no expander logic is used. 18. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled. 19. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
Document #: 38-03015 Rev. *B
Page 7 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS1 tS2 tH tWH tWL tRW tRR tRO tPR tPO tCF tP fMAX1 Description Dedicated Input to Combinatorial Output Delay[8] I/O Input to Combinatorial Output Delay[9] Dedicated Input to Combinatorial Output Delay with Expander Delay[10] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Mil Input to Output Enable Delay[5, 8] Input to Output Disable Delay[5, 8] Synchronous Clock Input to Output Delay Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Synchronous Clock to Local Feedback to Combinatorial Output[5, 12] Com'l/Ind Mil Dedicated Input or Feedback Set-Up Time to Synchronous Clock Com'l/Ind Input[8] Mil I/O Input Set-Up Time to Synchronous Clock Input[8, 13] Input Hold Time from Synchronous Clock Input[8] Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Asynchronous Clear Width[5, 8] Asynchronous Clear Recovery Time[5, 8] Asynchronous Clear to Registered Output Delay[8] Asynchronous Preset Recovery Time[5, 8] Asynchronous Preset to Registered Output Delay[8] Synchronous Clock to Local Feedback Input[5, 14] External Synchronous Clock Period (1/fMAX3)[5] External Maximum Frequency (1/(tCO1 + tS1))[5, 15] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 20 20 27 27 30 30 30 30 3 3 20 20 35 35 0 0 10 10 10 10 30 30 30 30 30 30 30 30 44 44 44 44 58 58 30 30 30 30 16 16 35 35
CY7C343
7C343-35 35 35 53 53 55 55 73 73 35 35 35 35 20 20 42 42 25 25 42 42 0 0 12.5 12.5 12.5 12.5 35 35 35 35 35 35 35 35 35 35 5 5 25 25 22.2 22.2 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. Max. Min. Max. Unit
I/O Input to Combinatorial Output Delay with Expander Delay[5, 11] Com'l/Ind
Document #: 38-03015 Rev. *B
Page 8 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30 Parameter fMAX2 fMAX3 fMAX4 tOH tPW Description Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + Com'l/Ind tCF)) or (1/tCO1)[5, 16] Mil Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), Com'l/Ind or (1/tCO1)[5, 17] Mil Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18] Output Data Stable Time from Synchronous Clock Input[5, 19] Asynchronous Preset Width[5, 8] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 43 43 50 50 50 50 3 3 30 30
CY7C343
7C343-35 33 33 40 40 40 40 3 3 35 35 ns ns MHz MHz MHz
Min. Max. Min. Max. Unit
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-20 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 Description Asynchronous Clock Input to Output Delay[8] Com'l/Ind Mil Asynchronous Clock Input to Local Feedback to Combinatorial Com'l/Ind Output[20] Mil Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[8] I/O Input Set-Up Time to Asynchronous Clock Input[8] Input Hold Time from Asynchronous Clock Input[8] Asynchronous Clock Input HIGH Time[8] Asynchronous Clock Input LOW Time[8, 21] Asynchronous Clock to Local Feedback Input[5, 22] External Asynchronous Clock Period (1/fMAXA4)[5] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com'l/Ind + tAS1)[5, 23] Mil 16 16 41.6 41.6 20 20 4 4 15 15 5 5 9 9 7 7 13 13 5 5 20 20 6 6 11 11 9 9 15 15 MHz ns ns ns ns ns Min. Max. 20 20 32 32 25 25 40 40 ns ns ns 7C343-25 Min. 12 Max. Unit ns
Notes: 20. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path.
Document #: 38-03015 Rev. *B
Page 9 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20 Parameter fMAXA2 fMAXA3 fMAXA4 tAOH Description Maximum Internal Asynchronous Frequency
[5, 24]
CY7C343
7C343-25 Min. 33 50 50 40 40 15 15 ns MHz MHz Max. Unit MHz
Min. Com'l/Ind Mil Com'l/Ind Mil 58.8 58.8 50 50 62.5 62.5 12 12
Max.
Data Path Maximum Frequency in Asynchronous Mode[5, 25]
Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com'l/Ind tAWL)[5, 26] Mil Output Data Stable Time from Asynchronous Clock Input[5, 27] Com'l/Ind Mil
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-30 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 fMAXA4 Description Asynchronous Clock Input to Output Delay[8] Com'l/Ind Mil Asynchronous Clock Input to Local Feedback to Combinatorial Com'l/Ind Output[20] Mil Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[8] I/O Input Set-Up Time to Asynchronous Clock Input[8] Input Hold Time from Asynchronous Clock Input[8] Asynchronous Clock Input HIGH Time[8] Asynchronous Clock Input LOW Time[8, 21] Asynchronous Clock to Local Feedback Input[5, 22] External Asynchronous Clock Period (1/fMAXA4)[5] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com'l/Ind + tAS1)[5, 23] Mil Maximum Internal Asynchronous Frequency[5, 24] Data Path Maximum Frequency in Asynchronous Mode[5, 25] Com'l/Ind Mil Com'l/Ind Mil Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com'l/Ind tAWL)[5, 26] Mil 25 25 27 27 40 40 33 33 40 40 6 6 25 25 8 8 14 14 11 11 18 18 30 30 23 23 33 33 28 28 33 33 MHz MHz MHz MHz Min. Max. 30 30 46 46 8 8 30 30 10 10 16 16 14 14 22 22 ns ns ns ns ns ns 7C343-35 Min. Max. Unit 35 35 55 55 ns ns ns
Notes: 24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. 25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input.
Document #: 38-03015 Rev. *B
Page 10 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30 Parameter tAOH Description Output Data Stable Time from Asynchronous Clock Input
[5, 27]
CY7C343
7C343-35 Min. 15 15 Max. Unit ns
Min. Com'l/Ind Mil 15 15
Max.
Internal Switching Characteristics Over Operating Range [7]
7C343-20 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay[28] Output Buffer Disable Delay Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Register Set-Up Time Relative to Clock Signal Com'l/Ind at Register Mil Register Hold Time Relative to Clock Signal at Com'l/Ind Register Mil Flow-Through Latch Delay Register Delay Transparent Mode Delay[29] Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Com'l/Ind Mil Com'l/ Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 6 6 6 6 12 12 2 2 4 4 4 4 2 2 1 1 2 2 8 8 8 8 14 14 2 2 ns ns ns Min. Max. 4 4 4 4 10 10 10 10 8 8 4 4 8 8 8 8 6 6 6 6 3 3 1 1 3 3 ns ns ns ns ns 7C343-25 Min. Max. 5 5 5 5 12 12 12 12 10 10 5 5 10 10 10 10 ns ns ns ns ns ns ns ns Unit ns
Notes: 28. Sample tested only for an output change of 500 mV. 29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
Document #: 38-03015 Rev. *B
Page 11 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-20 Parameter tFD tPRE tCLR tPCW tPCR tPIA Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Description Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Asynchronous Preset and Clear Pulse Width Com'l /Ind Mil Asynchronous Preset and Clear Recovery Time Com'l/Ind Mil Mil 4 4 4 4 12 12 Min. Max. 1 1 4 4 4 4 5 5 5 5
CY7C343
7C343-25 Min. Max. 1 1 5 5 5 5 ns ns 14 14 ns ns ns Unit ns
Programmable Interconnect Array Delay Time Com'l/Ind
Internal Switching Characteristics Over Operating Range [7]
7C343-30 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay[28] Output Buffer Disable Delay Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Register Set-Up Time Relative to Clock Signal Com'l/Ind at Register Mil Register Hold Time Relative to Clock Signal at Com'l/Ind Register Mil Flow-Through Latch Delay Register Delay Transparent Mode Delay[29] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 8 8 8 8 4 4 2 2 4 4 Min. Max. 7 7 5 5 14 14 14 14 12 12 5 5 11 11 11 11 10 10 12 12 4 4 2 2 4 4 ns ns ns ns 7C343-35 Min. Max. 9 9 7 7 20 20 16 16 13 13 6 6 13 13 13 13 ns ns ns ns ns ns ns ns Unit ns
Document #: 38-03015 Rev. *B
Page 12 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-30 Parameter tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Description Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Asynchronous Preset and Clear Pulse Width Com'l/Ind Mil Asynchronous Preset and Clear Recovery Time Com'l/Ind Mil Mil 6 6 6 6 16 16 Min. 10 10 10 10 16 16 2 2 1 1 6 6 6 6 7 7 7 7 Max.
CY7C343
7C343-35 Min. 12.5 12.5 12.5 12.5 18 18 3 3 2 2 7 7 7 7 ns ns 20 20 ns ns ns ns ns ns ns Max. Unit ns
Programmable Interconnect Array Delay Time Com'l/Ind
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT t PD1 /tPD2 COMBINATORIAL OUTPUT t ER COMBINATORIAL OR REGISTERED OUTPUT t ER HIGH-IMPEDANCE THREE-STATE VALID OUTPUT HIGH-IMPEDANCE THREE-STATE
Document #: 38-03015 Rev. *B
Page 13 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms (continued)
External Synchronous
DEDICATED INPUTS OR [8] REGISTERED FEEDBACK tS1 SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[8] tOH tRO/tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [12] tRW /tPW tRR /tPR tH t WH tWL
CY7C343
External Asynchronous
DEDICATEDINPUTSOR REGISTERED FEEDBACK [8 ] ASYNCHRONOUS CLOCK INPUT
tAS1
tAH
tAWH
tAWL
tACO1 tAOH
tRW/tPW
tRR/tPR
ASYNCHRONOUS CLEAR/PRESET [8 ]
tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK
Internal Combinatorial
tIN INPUT PIN tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
Document #: 38-03015 Rev. *B
Page 14 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB tFD tCLR,tPRE tFD tRH tAWH tAWL tF
CY7C343
Internal Synchronous
tCH SYSTEM CLOCK PIN tIN SYSTEM CLOCK AT REGISTER tRSU DATA FROM LOGIC ARRAY tRH tICS tCL
Output Mode
CLOCK FROM LOGIC ARRAY
tRD
tOD
DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE
Information
Speed (ns) 20 25 30 Ordering Code CY7C343-20JC/JI CY7C343-25HC/HI CY7C343-25JC/JI CY7C343-30HC/HI CY7C343-30JC/JI CY7C343-30HMB 35 CY7C343-35HC/HI CY7C343-35JC CY7C343-35HMB Package Name J67 H67 J67 H67 J67 H67 H67 J67 H67 Package Type 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier Military Military Commercial/Industrial Commercial/Industrial Operating Range Commercial/Industrial Commercial/Industrial
Document #: 38-03015 Rev. *B
Page 15 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters VOH VOL VIH VIL IIX IOZ ICC1 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Subgroups
CY7C343
Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Switching Characteristics
Parameters tPD1 tPD2 tPD3 tCO1 tS tH tACO1 tACO2 tAS tAH
Document #: 38-03015 Rev. *B
Page 16 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
CY7C343
51-80079-**
Document #: 38-03015 Rev. *B
Page 17 of 19
USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
CY7C343
51-85003-*A
Warp is a registered trademark, and Ultra37000, Warp Professional and Warp Enterprise are trademarks, of Cypress Semiconductor Corporation.
Document #: 38-03015 Rev. *B
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000TM FOR ALL NEW DESIGNS
Document History Page
Document Title: CY7C343 64-Macrocell MAX(R) EPLD Document Number: 38-03015 REV. ** *A *B ECN NO. 106315 122226 213375 Issue Date 04/24/01 12/28/02 See ECN Orig. of Change SZV RBI FSG Description of Change Change from Spec number: to 38-03015
CY7C343
Power up requirements added to Operating Range Information Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03015 Rev. *B
Page 19 of 19

▲Up To Search▲

Price & Availability of CY7C343

	To Download CY7C343 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .